Integrated circuit having capacitive elements

ABSTRACT

An integrated circuit having capacitive elements for smoothing a supply voltage is described. In this case, at least one additional metal electrode, which is configured as a high frequency-optimized capacitance and is distinguished by an extremely low sheet resistance, is connected in parallel with the MOS capacitances. By connecting the areally highly effective MOS capacitance, which, however, is connected with a somewhat higher impedance, in parallel with areally less effective metal capacitances, which, however, are connected to the supply voltage in a very low-impedance manner, it is possible to obtain broadband buffering and thus decoupling of high-frequency interference signals. Very high-frequency interference components are attenuated on the chip and do not pass into the system surrounding the integrated circuit.

CROSS-REFERENCE TO RELATED APPLICATION

This is a continuation of copending International Application No.PCT/DE99/03829, filed Dec. 1, 1999, which designated the United States.

BACKGROUND OF THE INVENTION Field of the Invention

The present invention relates to an integrated circuit having capacitiveelements for smoothing a supply voltage. Integrated circuits are knownin a multiplicity of embodiments and do not need to be explained infurther detail. The smoothing of the supply voltage of integratedcircuits by capacitors proves to be advantageous because the relevantintegrated circuits can, as a result, operate in a manner free frominterference and have a reduced electromagnetic emission. In this case,it is particularly advantageous, for reasons of area optimization inparticular, if the capacitors which are provided for smoothing arelikewise integrated in the integrated circuit. However, the capacitorsprovided in integrated circuits require a great deal of chip area incomparison with other integrated elements, which results in that therespective integrated circuit often becomes relatively large and hencealso expensive, susceptible to faults and unwieldy.

Japanese Patent Application JP 2-250 370 A describes an integratedcircuit in which the capacitors serving to smooth the supply voltage aredisposed underneath the corresponding supply tracks via which theintegrated circuit is supplied with the supply voltage. The capacitorsare formed there by the interaction of poly sections, formed in apolysilicon layer of the integrated circuit, and the substrate regionslying underneath. All or some of the negative accompanying phenomenadescribed above can be avoided in this way. In particular, the provisionof capacitors provided for smoothing the supply voltage does not mean,or at any rate does not necessarily mean, that an integrated circuitthat is constructed in such a way becomes larger than integratedcircuits which do not contain such capacitors. However, to date thecapacitors described in the Japanese Patent Application JP 2-250 370 Ahave, in many integrated circuits, not sufficed to smooth the supplyvoltage to the desired or required extent.

This is quite generally due to the fact that the so-called on-chipcapacitances described above have a very large resistive component intheir connection impedances, which results essentially from the highsheet resistances of the polysilicon or diffusion electrodes that areused in particular in the case of on-chip gate capacitances. This highresistive component in the connection impedances brings about a very lowdegree of attenuation at high frequencies, as a result of whichhigh-frequency AC voltage components can be emitted into the systemsurrounding the integrated circuit, where such electromagnetic emissionscan lead to interference with sensitive circuit elements.

SUMMARY OF THE INVENTION

It is accordingly an object of the invention to provide an integratedcircuit having capacitive elements that overcomes the disadvantages ofthe prior art devices of this general type.

Taking the prior art as a departure point, the present invention isbased on the object, therefore, of developing an integrated circuit ofthe generic type in such a way that the supply voltage of the circuitcan be smoothed in the best possible way, in particular even in the caseof high-frequency signals, without this being accompanied by anenlargement of the integrated circuit.

With the foregoing and other objects in view there is provided, inaccordance with the invention, an integrated circuit including a firstsupply track to be connected to a first supply potential and a secondsupply track to be connected to a second supply potential. The firstsupply potential and the second supply potential supply a supplyvoltage, and the first supply track and the second supply track form afirst metallic layer. At least one second metallic layer having at leastone third supply track to be connected to the first or second supplypotential is provided. The second metallic layer is disposed in eachcase above the first metallic layer. At least one first capacitiveelement is disposed below the first metallic layer and the at least onethird supply track and the first supply track and/or the second supplytrack define at least one second capacitive element. The first andsecond capacitive elements are provided for smoothing over the supplyvoltage.

The present invention makes it possible to provide, below the respectivesupply tracks, a maximum number of capacitors having an optimumefficiency. The total capacitance resulting from the parallel circuit ofthe respective capacitances is a maximum and can consequently smooth thesupply voltage as optimally as possible, in particular even in thehigh-frequency range of the integrated circuit, without this beingaccompanied by an enlargement of the integrated circuit.

Since the regions below the supply tracks are typically not utilized atall in conventional integrated circuits, the integrated circuit, as aresult of the integration of at least two capacitors which are connectedin parallel with one another, does not become larger, or at most becomesminimally larger, than would be the case if there were no capacitorintegration. The integrated circuit according to the invention cantherefore be accommodated on a minimum area.

Furthermore, the proximity of the capacitors to the supply tracks whichconduct the supply voltage to be smoothed makes it possible for theelectrical connections which are required in order to dispose thecapacitors effectively between the two poles of the supply voltage to beconfigured to be extremely short, as a result of which the integratedcircuit is simple in its structure and in its production and is alsoreliable in operation.

In accordance with an added feature of the invention, the at least onefirst capacitive element is connected in parallel with the at least onesecond capacitive element.

In accordance with an additional feature of the invention, the at leastone first capacitive element is one of a plurality of first capacitiveelements disposed below both the first supply track and below the secondsupply track, and the at least one second capacitive element is one of aplurality of second capacitive elements.

In accordance with another feature of the invention, the secondcapacitive elements each have a capacitance and the first capacitiveelements each have a capacitance at least a factor of 10 greater thanthe capacitance of the second capacitive elements.

In accordance with another added feature of the invention, a substratehaving doping regions formed therein is provided along with apolysilicon layer having at least one poly section disposed above thesubstrate. The first capacitive elements are formed by an interaction ofthe poly section formed in the polysilicon layer and the doping regionsformed in the substrate.

In accordance with another additional feature of the invention, aninsulating material is disposed between the poly section and the firstand second supply tracks. The insulating material has a plurality ofplated-through holes formed therein connecting the first supply track ofthe first metal layer to the poly section.

In accordance with yet another feature of the invention, the secondcapacitive element is formed by an interaction of the third supply trackand the first supply track.

In accordance with a further feature of the invention, the secondcapacitive element is formed by an interaction of the third supply trackand the second supply track.

In accordance with a further added feature of the invention, the firstcapacitive elements and the second capacitive elements each have acapacitive component and a resistive component connected in series withthe capacitive component. The resistive component of the secondcapacitive elements result from conductances of the first metallic layerand the at least one second metallic layer. The resistive component ofthe first capacitive elements result from conductances of the polysection and of corresponding ones of the doping regions in thesubstrate.

In accordance with a concomitant feature of the invention, the resistivecomponent of the first capacitive elements is at least a factor of 10greater than the resistive component of the second capacitive elements.

Other features which are considered as characteristic for the inventionare set forth in the appended claims.

Although the invention is illustrated and described herein as embodiedin an integrated circuit having capacitive elements, it is neverthelessnot intended to be limited to the details shown, since variousmodifications and structural changes may be made therein withoutdeparting from the spirit of the invention and within the scope andrange of equivalents of the claims.

The construction and method of operation of the invention, however,together with additional objects and advantages thereof will be bestunderstood from the following description of specific embodiments whenread in connection with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagrammatic, sectional view of a basic structure of anintegrated circuit having capacitive elements provided for smoothing asupply voltage according to the invention, wherein a second capacitiveelement is formed by an interaction of the second supply track and thethird supply track;

FIG. 2a is a circuit diagram for the elements of the integrated circuitshown in FIG. 1 and FIG. 3;

FIG. 2b is a graph showing associated impedance curves of the integratedcircuit; and

FIG. 3 is a diagrammatic, sectional view of a basic structure of anintegrated circuit having capacitive elements provided for smoothing asupply voltage according to the invention, wherein a second capacitiveelement is formed by an interaction of the first supply track and thethird supply track.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

In all the figures of the drawing, sub-features and integral parts thatcorrespond to one another bear the same reference symbol in each case.Referring now to the figures of the drawing in detail and first,particularly, to FIG. 1 thereof, there is shown schematically, in asectional view, a basic structure of an integrated circuit havingcapacitive elements provided for smoothing a supply voltage. With regardto FIG. 1, it should be noted at the outset that FIG. 1—even though itis a sectional view—does not depict any hatching for reasons of clarity.

The integrated circuit that is considered in the present case may be anykind of integrated circuit, in particular a CMOS circuit. FIG. 1 merelypartially illustrates a portion of the integrated circuit. In this case,the integrated circuit is integrated in a substrate S, which, forexample, may be a semiconductor body composed of silicon. Disposed abovethe substrate S at a first distance D1 is a poly layer P, composed ofpolysilicon for example. Provided above the poly layer P is a firstmetal layer M1 disposed at a distance. Provided above the first metallayer M1 at a second distance D2 is a second metal layer M2.

The exemplary embodiment in FIG. 1 thus shows the two metal layers M1,M2 and the poly layer P lying underneath.

However, this does not preclude the possibility of still further metallayers and/or further poly layers being provided above the substrate Shaving the integrated circuit. The interspaces between the individuallayers and/or the substrate S are filled by an insulating material 20which typically contains silicon dioxide.

The structures of the first metal layer M1 that are shown are a firstsupply track 1, which is connected to a first supply potential V1, and asecond supply track 2, which is connected to a second supply potentialV2. Via the first and the second supply tracks 1, 2, the supply voltageis fed to those locations in the integrated circuit at which the supplyvoltage is required. In this case, by way of example, the first supplypotential V1 may be a VDD potential and the second supply potential V2may be a VSS supply potential. The second metal layer M2 contains athird supply track 3, which is likewise connected to the first supplypotential V1 in the exemplary embodiment shown.

The poly layer P contains one or more poly sections 4 and is connectedto the first supply track 1 via first plated-through holes 5. The secondsupply track 2 is connected to the substrate S via second plated-throughholes 6.

The first supply track 1 is thus coupled via the poly section 4 in aknown manner via a first capacitive element (first capacitor) 11 to thesubstrate S and thus to the second supply track 2. As will be describedin more detail, the first capacitor 11 is disposed essentially below thesupply tracks 1,2 and is formed by the interaction of the poly section 4and the substrate S.

According to the invention, moreover, at least one second capacitiveelement (second capacitor) 12 is provided, which is formed from theinteraction of the second supply track 2 and the third supply track 3.

In the exemplary embodiment as shown in FIG. 1, the semiconductor bodycontains the n-doped substrate S. It goes without saying that it wouldalso be conceivable to use a p-doped or undoped substrate S. A p-dopedwell 7 is embedded in the substrate S. The well 7 may have beenintroduced into the substrate S by a diffusion process, by ionimplantation with an optionally subsequent thermal step, by ofdeposition, etc.

At least one zone 9 is embedded in the well 7 at a surface 8 of thesubstrate S. The zone 9 is heavily n-doped in the present exemplaryembodiment. In this case, the zone 9 may likewise have been introducedinto the well 7 by diffusion or ion implantation, as described above.

Typically, but not necessarily, the first zone 9 constitutes a channelimplantation or a channel diffusion for the integrated circuitfabricated using CMOS technology or for the gate capacitances 11 of theintegrated circuit.

The zone 9 is connected to the second supply track 2 via the secondplated-through holes 6. The aforementioned zone 9 and the secondplated-through holes 6 thus form the substrate contacts, the functionand method of operation of which are known and do not require anyfurther explanations.

In accordance with the illustration in FIG. 1, the two capacitors 11, 12are provided, as already described, the first of which is provided belowthe supply tracks 1 and 2 and the second of which is provided above thesupply track 2. The structure and the configuration of the capacitors11, 12 described are, as has already been mentioned above, illustratedonly in a highly diagrammatic fashion in FIG. 1.

The first capacitor 11 situated below the supply tracks 1 and 2 isformed by the poly section 4, the zone 9 provided underneath in thesubstrate S or the well 7, and the insulating material 20 lying inbetween. The second capacitor 12 is formed by the overlapping areas ofthe second and third supply tracks 2, 3 and the insulating material 20situated in between.

As is evident from FIG. 1, the first capacitor 11 provided for smoothingthe supply voltage is situated essentially below the supply tracks 1, 2.The poly section 4, which to a certain extent constitutes one of thecapacitor plates, is likewise essentially disposed below the supplytracks 1, 2.

Particularly if the poly section 4 of the first capacitor 11 has a verylarge area, it is advantageous if the poly section 4 is connected to thefirst supply track 1 via a multiplicity of the first plated-throughholes 5, which are advantageously disposed at the same distance from oneanother and in a row. As a result, the real parts of the capacitorimpedances can be kept low, which is highly significant in particularfor the high-frequency behavior of the capacitors 11.

Furthermore, it proves to be particularly favorable if approximatelyequal parts of the non-reactive resistance of the first capacitor 11 arecaused by the zone 9 and the poly section 4. Typically, but notnecessarily, the regions of the zone 9 that are illustrated in FIG. 1are configured to have considerably larger areas than the relevant polysection 4.

The same applies correspondingly, of course, to the second supply track2 as well; in this case, it is advantageous, in particular also forreasons of effectiveness, if the second supply track 2 is essentiallycovered by a single, large-area, namely the third, supply track 3. Sincethe second and third supply tracks 2, 3 are typically configured to bemetallic, the real part or the resistive component in the capacitorimpedance of the second capacitor 12 is, as a rule, negligible comparedwith the imaginary part thereof.

The schematic illustration in FIG. 1 illustrates merely a single polysection 4 and a single supply track 1, 2, 3 in each case. It goeswithout saying that an integrated circuit may have a multiplicity ofsuch supply tracks 1, 2, 3 and also a multiplicity of poly sections 4.Typically, however, the separate zone 9 need not be assigned to eachpoly section 4; it is also possible to provide a single, large zone 9for all the poly sections 4.

The configuration of the capacitors 11, 12 below the supply tracks 1, 2,3 proves to be advantageous in a number of respects. First, because thisspace in an integrated circuit is not usually utilized in other ways andthe configuration of the capacitors 11, 12 at this location consequentlydoes not lead to an enlargement of the integrated circuit.

Secondly, it is advantageous that the indispensable connections betweenthe supply tracks 1, 2, 3 and the capacitors 11, 12, wherever the latterare provided, can consequently be produced in a particularly simple andelegant manner.

For the structure shown in FIG. 1, therefore, an equivalent circuitdiagram is produced which is described in more detail below withreference to FIGS. 2a and 2b.

The parallel circuit formed by the first capacitor 11 and the secondcapacitor 12 and illustrated in FIG. 2a thus results from the structureshown in FIG. 1. The capacitors 11, 12 are typically to be regarded asnot ideal, i.e. in addition to a capacitive component they also have aninductive and resistive component. A series circuit formed by a firstcapacitance C_(MOS), a first inductance L_(MOS) and a first resistanceR_(MOS) thus results for the first capacitor 11, which is also referredto as MOS capacitor below. The impedance Z_(MOS)(S) of the MOS capacitor11 is calculated in known fashion as follows:${Z_{MOS}(S)} = {R_{MOS} + {S \cdot L_{MOS}} + \frac{1}{S \cdot C_{MOS}}}$

-   -   In this case, S designates the complex frequency parameters        S=σ+jω.

A series circuit formed by a second capacitance C_(MET), secondinductance L_(MET) and second resistance R_(MET) results in anequivalent manner for the second capacitor 12, which is referred to as ametal capacitor below. The corresponding impedance Z_(MET)(S) of themetal capacitor 12 is calculated in an equivalent manner as follows:${Z_{MET}(S)} = {R_{MET} + {S \cdot L_{MET}} + \frac{1}{S \cdot C_{MET}}}$

The first series circuit resulting from the elements of the MOScapacitor 11 and the second series circuit resulting from the elementsof the metal capacitor 12 are connected in parallel with one another.Consequently, the total impedance Z(S) for this parallel circuit turnsout to be ${Z(S)} = \frac{Z_{MOS} \cdot Z_{MET}}{Z_{MOS} + Z_{MET}}$

The parallel circuit formed by the first series circuit and the secondseries circuit is in this case disposed between the first supplypotential V1 and the second supply potential V2.

The particular advantage of the parallel circuit is that the firstcapacitive element C_(MOS) is dimensioned to be very much larger thanthe second capacitive element C_(MET). This is due in particular to thefact that the plate separation D1 of the first capacitive elementC_(MOS) is generally considerably smaller than the plate separation D2of the second capacitive element C_(MET), which accordingly results inthat the first capacitor 11 has a much larger capacitance than thesecond capacitor 12. In this case, D1 usually designates the plateseparation of a gate capacitance; in the case of an integrated circuit,depending on the technology used, D1 varies in the range of a fewnanometers (e.g. 5-15 nm). In comparison with this, the plate separationD2 is typically at least a factor of 10 greater than the plateseparation D1 (e.g. D2≧100 nm).

The inductive elements L_(MOS), L_(MET) result from the fact that thecorresponding capacitive elements C_(MOS), C_(MET) generally do notconstitute ideal capacitances; rather, real capacitances also quitegenerally have a non-negligible inductive component which becomesincreasingly apparent in particular in the high-frequency region of theimpedance curve.

The first resistive element R_(MOS) results essentially from theresistance of the poly section 4 and also from the sum of the diffusionresistances of the zones 7, 9. The corresponding conductances of thesupply tracks 1, 2 are small by comparison therewith and can generallybe disregarded.

The second resistive element R_(MET) results essentially from theresistances of the supply tracks 2, 3. Ideally, the resistance of thesecond resistive element R_(MET) is virtually zero and can bedisregarded compared with the very much larger resistance of the firstresistive element R_(MOS).

The respective impedance curves as a function of the frequency f areillustrated in FIG. 2b. In this case, the curve designated by (B)designates the impedance curve for the MOS capacitor 11 and the curvedesignated by (A) designates the impedance curve for the metal capacitor12. The solid bold curve (C) then designates the total impedance curvefor the parallel circuit formed by the two capacitors 11, 12 inaccordance with FIG. 2a.

The total impedance curve (bold curve (C) in FIG. 2b) resulting from theparallel circuit exhibits a considerable improvement in the frequencyresponse or in the attenuation response since particularly thelow-impedance range between capacitive and inductive components has beensignificantly widened. As is known, the capacitive component ispredominant in the low-frequency range through to the minimum of theimpedance curve being reached, while the inductive component ispredominant in the succeeding, higher-frequency range. This behavioraffords a considerable increase in the effectiveness of combinedMOS/metal capacitances compared with a single, pure MOS capacitance. TheMOS capacitance acts at very low frequencies in the range below 200 MHz,and the metal capacitance acts at higher frequencies.

Consequently, a parallel circuit of at least two capacitances 11, 12 ofthis type enables broadband buffering and decoupling of high-frequencyinterference signals. By connecting an areally highly effective MOScapacitance 11, which, however, is connected with a somewhat higherimpedance, in parallel with an areally less effective metal capacitance,which, however, is connected to the supply voltage in a verylow-impedance manner, it is possible to obtain broadband buffering andthus decoupling of high-frequency interference signals. Veryhigh-frequency interference components are thus attenuated on the chipand no longer pass into the system surrounding the integrated circuit.

Although the structure illustrated in FIG. 1 is currently regarded asthe simplest capacitor configuration according to the invention, thisshould not be understood as a restriction of the invention. Inprinciple, the capacitors 11, 12 can also be disposed arbitrarilydifferently below the supply tracks 1, 2, 3. It is particularlyadvantageous, however, if the first capacitor 11 and/or the secondcapacitor 12 are connected with the largest possible area.

The present invention has been explained in particular using a simplesingle MOS capacitance 11. It goes without saying, however, that theinvention can also be extended to arbitrary integrated circuits,configured for example using CMOS technology, with however many of suchMOS capacitors 11 as are desired. Integrated circuits configured usingCMOS technology, in particular, typically have at least two of these MOScapacitances, which are constructed such that they are mutuallycomplementary.

Furthermore, the present invention has been explained using the singlemetal capacitance 12 connected in parallel with the single MOScapacitance 11. In particular, it is also particularly advantageous if aplurality of metal capacitors 12 according to the invention areconnected in parallel with each MOS capacitor 11. In particular, byvirtue of the dimensioning of the MOS capacitors 11 and the metalcapacitors 12 of the parallel circuit, the latter can be optimallyadapted to the respective frequency spectrum and, consequently, verybroadband buffering can be achieved.

The structure shown in FIG. 3 is almost identical with that in FIG. 1,except that the second capacitive element is formed by an interaction ofthe first supply track 1 and the third supply track 3. The abovedescription in connection with FIG. 1 is also applicable to FIG. 3.

In summary and in conclusion, it may be emphasized that the integratedcircuit described can be accommodated on a minimal area in a very simplemanner.

1. An integrated circuit, comprising: a first supply track to beconnected to a first supply potential; a second supply track to beconnected to a second supply potential, the first supply potential andthe second supply potential supplying a supply voltage, said firstsupply track and said second supply track forming a first metalliclayer; at least one second metallic layer having at least one thirdsupply track to be connected to one of the first supply potential andthe second supply potential and disposed in each case above said firstmetallic layer; at least one first capacitive element disposed belowsaid first metallic layer; and at least one second capacitive elementdefined by said at least one third supply track and at least one of saidfirst supply track and said second supply track; said at least one firstcapacitive element and said at least one second capacitive element beingconnected in parallel and smoothing over the supply voltage; said atleast one first capacitive element being one of a plurality of firstcapacitive elements disposed below both said first supply track and saidsecond supply track, and said at least one second capacitive elementbeing one of a plurality of second capacitive elements; said secondcapacitive elements each having a capacitance and said first capacitiveelements each having a capacitance being at least a factor of 10 greaterthan said capacitance of said second capacitive elements.
 2. Theintegrated circuit according to claim 1, including: a substrate havingdoping regions formed therein; and a polysilicon layer having at leastone poly section disposed above said substrate, said first capacitiveelements formed by an interaction of said at least one poly sectionformed in said polysilicon layer and said doping regions formed in saidsubstrate.
 3. The integrated circuit according to claim 2, including aninsulating material disposed between said at least one poly section andsaid first and second supply tracks, said insulating material having aplurality of plated-through holes formed therein connecting said firstsupply track of said first metal layer to said at least one polysection.
 4. The integrated circuit according to claim 1, wherein said atleast one second capacitive element is formed by an interaction of saidat least one third supply track and said first supply track.
 5. Theintegrated circuit according to claim 1, wherein said at least onesecond capacitive element is formed by an interaction of said at leastone third supply track and said second supply track.
 6. The integratedcircuit according to claim 2, wherein said first capacitive elements andsaid second capacitive elements each have a capacitive component and aresistive component connected in series with said capacitive component,said resistive component of said second capacitive elementssubstantially resulting from conductances of said first metallic layerand said at least one second metallic layer, and said resistivecomponent of said first capacitive elements substantially resulting fromconductances of said at least one poly section and of corresponding onesof said doping regions in said substrate.
 7. The integrated circuitaccording to claim 6, wherein said resistive component of said firstcapacitive elements is at least a factor of 10 greater than saidresistive component of said second capacitive elements.
 8. An integratedcircuit, comprising: a first supply track to be connected to a firstsupply potential; a second supply track to be connected to a secondsupply potential, the first supply potential and the second supplypotential supplying a supply voltage, said first supply track and saidsecond supply track forming a first metallic layer; at least one secondmetallic layer having at least one third supply track to be connected toone of the first supply potential and the second supply potential anddisposed in each case above said first metallic layer; a substratehaving doping regions formed therein; a polysilicon layer having atleast one poly section disposed above said substrate; at least one firstcapacitive element disposed below said first metallic layer, formed byan interaction of said at least one poly section formed in saidpolysilicon layer and said doping regions formed in said substrate; andat least one second capacitive element defined by said at least onethird supply track and at least one of said first supply track and saidsecond supply track; said at least one first capacitive element and saidat least one second capacitive element being connected in parallel andsmoothing over the supply voltage; said at least one first capacitiveelement being one of a plurality of first capacitive elements disposedbelow both said first supply track and said second supply track, andsaid at least one second capacitive element being one of a plurality ofsecond capacitive elements; said first capacitive elements and saidsecond capacitive elements each having a capacitive component and aresistive component connected in series with said capacitive component,said resistive component of said second capacitive elementssubstantially resulting from conductances of said first metallic layerand said at least one second metallic layer, and said resistivecomponent of said first capacitive elements substantially resulting fromconductances of said at least one poly section and of corresponding onesof said doping regions in said substrate; said resistive component ofsaid first capacitive elements being at least a factor of 10 greaterthan said resistive component of said second capacitive elements.
 9. Theintegrated circuit according to claim 8, wherein said capacitivecomponent of said first capacitive elements is at least a factor of 10greater than said capacitive component of said second capacitiveelements.
 10. The integrated circuit according to claim 8, including aninsulating material disposed between said at least one poly section andsaid first and second supply tracks, said insulating material having aplurality of plated-through holes formed therein connecting said firstsupply track of said first metal layer to said at least one polysection.
 11. The integrated circuit according to claim 8, wherein saidat least one second capacitive element is formed by an interaction ofsaid at least one third supply track and said first supply track. 12.The integrated circuit according to claim 8, wherein said at least onesecond capacitive element is formed by an interaction of said at leastone third supply track and said second supply track.